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this is information on a product in full production. june 2013 docid18279 rev 5 1/37 st1cc40 3 a monolithic step-down curre nt source with synchronous rectification datasheet - production data features ? 3.0 v to 18 v operating input voltage range ? 850 khz fixed switching frequency ? 100 mv typ. current sense voltage drop ? 6 ? a standby current in inhibit mode ? ?? 7% output current accuracy ? synchronous rectification ? 95 m ?? hs / 69 m ? ls typical r ds(on) ? peak current mode architecture ? embedded compensation network ? internal current limiting ? ceramic output capacitor compliant ? thermal shutdown applications ? battery charger ? signage ? emergency lighting ? high brightness led driving ? general lighting description the st1cc40 device is an 850 khz fixed switching frequency monolithic step-down dc-dc converter designed to operate as precise constant current source wi th an adjustable current capability up to 3 a dc . the regulated output current is set connecting a sensing resistor to the feedback pin. the embedded synchronous rectification and the 100 mv typical r sense voltage drop enhance the efficiency performance. the size of the overall application is minimized thanks to the high switching frequency and ceramic output capacitor compatibility. the device is fully protected against thermal overheating, overcurrent and output short-circuit. inhibit mode minimizes the current consumption in standby. the st1cc40 is available in vfqfpn8 4 mm x 4 mm 8-lead, and standard so8 package. vfqfpn8 4x4 figure 1. typical application circuit #). #&,4 6). '.$ ).( 23 34## 6).?! ).( &" !'.$ 0'.$ 37 6).?37 %0 #/54 , , !-v www.st.com
table of contents st1cc40 2/37 docid18279 rev 5 table of contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.5 inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.6 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 g co (s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 led small signal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5 total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.6 edesign studio software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1.1 sensing resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1.2 inductor and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1.3 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid18279 rev 5 3/37 st1cc40 table of contents 37 7.2 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
list of tables st1cc40 4/37 docid18279 rev 5 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. list of ceramic capacitors for the st1cc40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. vfqfpn8 (4 x 4 x 1.08 mm) package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. so8-bw package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
docid18279 rev 5 5/37 st1cc40 list of figures 37 list of figures figure 1. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. st1cc40 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. transconductance embedded error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. equivalent series resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. load equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. edesign studio screenshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14. switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. constant current protection triggering hiccup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16. demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. pcb layout (component side) vfqfpn8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. pcb layout (bottom side) vfqfpn8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19. pcb layout (component side) so8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 20. pcb layout (bottom side) so8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 21. soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 22. inhibit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 23. thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 24. hiccup current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 25. ocp blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 26. current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 27. vfqfpn8 (4 x 4 x 1.08 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 28. so8-bw package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
pin settings st1cc40 6/37 docid18279 rev 5 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description 6: 3*1' 9,1$ 9,16: *1' $*1' )% 1& 9)4)31 62 %: ,1+ ,1+ $0y table 1. pin description no. type description vfqfpn8 s08-bw 13vin a analog circuitry power supply connection 24inh inhibit input pin. low signal level disables the device. leave this pin floating if not used 35fb feedback input. connect a proper sensing resistor to set the led current 4 6 agnd analog circuitry ground connection 5 - nc not connected 68v insw power input voltage 7 1 sw regulator switching pin 8 2 pgnd power ground - 7 gnd connect to agnd
docid18279 rev 5 7/37 st1cc40 maximum ratings 37 2 maximum ratings 3 thermal data table 2. absolute maximum ratings symbol parameter value unit v insw power input voltage -0.3 to 20 v v ina input voltage -0.3 to 20 v inh inhibit voltage -0.3 to v ina v sw output switching voltage -1 to v in v pg power good -0.3 to v in v fb feedback voltage -0.3 to 2.5 i fb fb current -1 to +1 ma p tot power dissipation at t a < 60 c 2 w t op operating junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction-ambient (1) 1. package mounted on demonstration board. vfqfpn8 40 c/w so8-bw 65
electrical characteristics st1cc40 8/37 docid18279 rev 5 4 electrical characteristics t j = 25 c, v cc = 12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test conditions value unit min. typ. max. v in operating input voltage range see (1) 318 v device on level 2.6 2.75 2.9 device off level 2.4 2.55 2.7 v fb feedback voltage t j = 25 c 90 97 104 mv t j = 125 c 90 100 110 i fb v fb pin bias current 600 na r dson -p high-side switch on-resistance i sw = 750 ma 95 m ? r dson -n low-side switch on-resistance i sw = 750 ma 69 m ? i lim maximum limiting current see (2) 5a oscillator f sw switching frequency 0.7 0.85 1 mhz d duty cycle see (2) 0 100 % dc characteristics i q quiescent current duty cycle = 0 v fb > 100 mv 1.5 2.5 ma i qst-by total standby quiescent current off 2.4 4.5 ? a see (1) 6 inhibit v inh inh threshold voltage device on level 1.2 v device off level 0.4 i inh inh current 2 ? a soft-start t ss soft-start duration 1 ms protection t shdn thermal shutdown 150 c hystereris 15 1. specifications referred to t j from -40 to +125 c. specifications in the -40 to +125 c temperature range are assured by design, characterization and statistical correlation. 2. guaranteed by design.
docid18279 rev 5 9/37 st1cc40 functional description 37 5 functional description the st1cc40 device is based on a ?peak current mode? architecture with fixed frequency control. as a consequence, the intersection between the error amplifier output and the sensed inductor current generates the control signal to drive the power switch. the main internal blocks shown in the block diagram in figure 3 are: ? high-side and low-side embedded power element for synchronous rectification ? a fully integrated sawtooth osc illator with a typical frequency of 850 khz ? a transconductance error amplifier ? a high-side current sense amplifier to track the inductor current ? a pulse width modulator (pwm) comparator and the circuitry necessary to drive the internal power element ? the soft-start circuitry to decrease the inrush current at power-up ? the current limitation circuit based on t he pulse-by-pulse current protection with frequency divider ? the inhibit circuitry ? the thermal protection function circuitry figure 3. st1cc40 block diagram 9,1$ 9,16: 26& ($ '5,9(5 '5,9(5 '0' 273 026)(7 &21752/ /2*,& 5(*8/$725 ,1+,%,7 6(16( &203 &203 2&3 5() 9 62)767$57 9vxp 9f 2&3 89/2 9guy b s 9guy bq , 9 5 6(16( 6: *1'3 *1'$ ,1+ )% $0y
functional description st1cc40 10/37 docid18279 rev 5 5.1 power supply an d voltage reference the internal regulator circuit consists of a startup circuit, an internal voltage pre-regulator, the bandgap voltage reference and the bias blo ck that provides curren t to all the blocks. the starter supplies the startup current to the entire device when the input voltage goes high and the device is enabled (inhibit pin con nected to ground). the pre-regulator block supplies the bandgap cell with a pre-regulated voltage that has a very low supply voltage noise sensitivity. 5.2 voltage monitor an internal block continuously senses the v cc , v ref and v bg . if the monitored voltages are good, the regulator begins operating. there is also a hysteresis on the v cc (uvlo). figure 4. internal circuit 5.3 soft-start the startup phase is implemented ramping the reference of the embedded error amplifier in 1 msec typ. time. it minimizes the inrush current and decreases the stress of the power components at power-up. during normal operation a new soft-start cycle takes place in case of: ? thermal shutdown event ? uvlo event. 5.4 error amplifier the voltage error amplifier is the core of the loop regulation. it is a transconductance operational amplifier whose no n-inverting input is connecte d to the internal voltage reference (100 mv), while the in verting input (fb) is connected to the output current sensing resistor. the error amplifier is internally compensated to minimize the size of the final application. starter preregulator ic bias bandgap vref vreg vcc d00in126 am12803v1
docid18279 rev 5 11/37 st1cc40 functional description 37 the error amplifier output is compared with the inductor current sense information to perform pwm control. 5.5 inhibit the inhibit block disables most of the circuitr y when the inh input signa l is low. the current drawn from the input voltage is 6 a typical in inhibit mode. 5.6 thermal shutdown the shutdown block generates a signal that disa bles the power stage if the temperature of the chip goes higher than a fixed internal th reshold (150 10 c typical). the sensing element of the chip is close to the pdmos area, ensuring fast and accurate temperature detection. a 15 c typical hysteresis prev ents the device from turning on and off continuously during the protection operation. table 5. uncompensated error amplifier characteristics description value transconductance 250 s low frequency gain 96 db c c 195 pf r c 70 k ?
application notes st1cc40 12/37 docid18279 rev 5 6 application notes 6.1 closing the loop figure 5. block diagram of the loop 6.2 g co (s) control to output transfer function the accurate control to output transfer function for a buck peak current mode converter can be written as: equation 1 where r 0 represents the load resistance, r i the equivalent sensing resistor of the current sense circuitry, ? p the single pole introduced by the lc filter and ? z the zero given by the esr of the output capacitor. f h (s) accounts for the sampling effect performe d by the pwm comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. 9 ,1 /&ilowhu 9 5() huuru dpsolilhu )% frpshqvdwlrq qhwzrun 3:0 frpsdudwru +6 vzlwfk 5 6 / & 287 5 & & & 3:0frqwuro &xuuhqwvhqvh /6 vzlwfk 9 287 9 &21752/ * &2 v $ 2 v . /(' $0y g co s ?? r 0 r i ------ - 1 1 r 0 t sw ? l ---------------------- - m c 1d ? ?? 0,5 ? ? ?? ? + ---------------------------------------------------------------------------------------- 1 s ? z ------ + ?? ?? 1 s ? p ------ + ?? ?? --------------------- - f h s ?? ??? =
docid18279 rev 5 13/37 st1cc40 application notes 37 equation 2 equation 3 where: equation 4 s n represents the slope of the sensed inductor current, s e the slope of the external ramp (v pp peak-to-peak amplitude) that implements the slope compensation to avoid sub- harmonic oscillations at duty cycle over 50%. the sampling effect contribution f h (s) is: equation 5 where: equation 6 and equation 7 6.3 error amplifier compensation network the st1cc40 device embeds the error amplifier (see figure 6 ) and a pre-defined compensation network which is ef fective in stabilizing the system in most of the application conditions. ? z 1 esr c out ? ------------------------------- = ? p 1 r load c out ? ------------------------------------- - m c 1d ? ?? 0,5 ? ? lc out f sw ?? --------------------------------------------- + = m c 1 s e s n ------ + = s e v pp f sw ? = s n v in v out ? l ----------------------------- - r i ? = ? ? ? ? ? ? ? ? ?? 1 1 s ? n q p ? ------------------ - s 2 ? n 2 ------ ++ ------------------------------------------ - = ? n ? f sw ? = q p 1 ? m c 1d ? ?? 0,5 ? ? ?? ? ---------------------------------------------------------- =
application notes st1cc40 14/37 docid18279 rev 5 figure 6. transconductance embedded error amplifier r c and c c introduce a pole and a zero in the open loop gain. c p does not significantly affect system stability but it is useful to reduce th e noise at the output of the error amplifier. the transfer function of the error amplifier and its compensation network is: equation 8 where a vo = g m r o . the poles of this transfer function are (if c c >> c 0 + c p ): equation 9 equation 10 whereas the zero is defined as: equation 11 & 3 5 & & & )% &203 g9 5 * p g9 9 ($ 5 & & & & 3 & $0y a 0 s ?? a v0 1s + r c c c ?? ?? ? s 2 r 0 c 0 c p + ?? r c c c sr 0 c c ? r 0 c 0 c p + ?? r c c c ? + ? + ?? 1 + ? + ?? ?? ------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------- = f p lf 1 2 ? r 0 c c ?? ? --------------------------------- - = f p hf 1 2 ? r c c 0 c p + ?? ?? ? ---------------------------------------------------- = f z 1 2 ? r c c c ?? ? --------------------------------- =
docid18279 rev 5 15/37 st1cc40 application notes 37 the embedded compensation network is r c = 70 k, c c = 195 pf while c p and c o can be considered as negligible. the error amplifier output resistance is 240 m ?? so the relevant singularities are: equation 12 6.4 led small signal model once the system reaches the working condit ion the leds composing the row are biased and their equivalent circuit can be considered as a resistor for frequencies << 1 mhz. the led manufacturer typically provides the equivalent dynamic resistance of the led biased at different dc current. this parameter is required to study the behavior of the system in the small signal analysis. for instance, the equivalent dynamic resistance of luxeon iii star fr om lumiled measured with a different biasing current level is reported below: in case the led datasheet doesn?t report the equi valent resistor value, it can be simply derived as the tangent to the diode i-v charac teristic in the present working point (see figure 7 ). figure 7. equivalent series resistor f z 11 6 khz ? = f p lf 34 hz ? = r led 1,3 ? i led 350ma = 0,9 ? i led 700ma = ? ? ? >9@ >$@ zrunlqjsrlqw $0y
application notes st1cc40 16/37 docid18279 rev 5 figure 8 shows the equivalent circuit of th e led constant current generator. figure 8. load equivalent circuit as a consequence, the led eq uivalent circuit gives the ? led (s) term correlating the output voltage with the high impedance fb input: equation 13 6.5 total loop gain in summary, the open loop gain can be expressed as: equation 14 example design specifications: v in = 12 v, v fw_led = 3.5 v, n led = 2, r led = 1.1 ? , i led = 700 ma, i led ripple = 2% the inductor and capacitor value are dimensioned in order to meet the i led ripple specifications (see section 7.1.2 for output capacitor and inductor selection guidelines ): l = 10 ? h, c out = 2.2 ? f mlcc (negligible esr) 9,1 5g &287 / / 5g 5v 'ohg 5v ' ' &287 9,1 / / 'ohg $0y ? led n led ?? r sense n led r led r sense + ? --------------------------------------------------------- - = gs ?? g co s ?? a 0 s ?? ? led n led ?? ?? =
docid18279 rev 5 17/37 st1cc40 application notes 37 accordingly, with section 7.1.1 the sensing resistor value is: equation 15 equation 16 the gain and phase margin bode diagrams are plotted respectively in figure 9 and figure 10 . figure 9. module plot r s 100 mv 700 ma -------------------- - 140 m ? ? = ? led n led ?? r sense n led r led r sense + ? --------------------------------------------------------- - = 140 m ? 21,1 ? ? 140 m ? + ------------------------------------------------- 0,06 == *v g% (;7(51$//22302'8/( )uhtxhqf\>+]@ 0rgxoh>g%@ $0y
application notes st1cc40 18/37 docid18279 rev 5 figure 10. phase plot the cutoff frequency and the phase margin are: equation 17 6.6 edesign studio software the st1cc40 device is supported by the edesign software which can be seen online on the stmicroelectronics ? home page (www.st.com). *v (;7(51$//223*$,13+$6( )uhtxhqf\>+]@ 3kdvh $0y f c 100 khz = pm 47 ? =
docid18279 rev 5 19/37 st1cc40 application notes 37 figure 11. edesign studio screenshot the software easily supports the component sizing according to the technical information given in this datasheet (see section 6 ). the final user is requested to fill in the requested informat ion such as the input voltage range, the selected led parameters and the number of leds composing the row. the software calculates external components according to the internal database. it is also possible to define new components and ask the software to have them used. bode plots, estimated efficiency an d thermal performance are provided. finally, the user can save the des ign and print all the information including the bill of material of the board.
application information st1cc40 20/37 docid18279 rev 5 7 application information 7.1 component selection 7.1.1 sensing resistor in closed loop operation the st1cc40 feedba ck pin voltage is 100 mv so the sensing resistor calculation is expressed as: equation 18 since the main loop (see section 6.1 ) regulates the sensing resistor voltage drop, the average current is regulated into the leds. the integration period is at minimum 5 * t sw since the system bandwidth can be dimensioned up to f sw /5 at maximum. the system performs the output current regulation over a period which is at least five times longer than the switching frequency. the output current regulation neglects the ripple current contribution and its reliance on external parameters like input voltage and output voltage variations (line transient and led forward voltage spread). this performance can not be achieved with simpler regulation loops like a hysteretic control. for the same reason the switching frequency is constant over the application conditions, that helps to tune the emi filtering and to guarantee the maximum led current ripple specifications in the applicat ion range. this performance ca nnot be achieved using constant on/off-time architecture. 7.1.2 inductor and out put capacitor selection the output capacitor filters the inductor curr ent ripple that, given the application conditions, depends on the inductor value. as a consequenc e, the led current ripple, that is the main specification for a switching current source, d epends on the inductor and output capacitor selection. figure 12. equivalent circuit r s 100 mv i led -------------------- = '&5 '&5 &287 5v 9,1 / (65 5g 9,1 / (65 'ohg ' &287 ' 5v 5gq 'ohgq $0y
docid18279 rev 5 21/37 st1cc40 application information 37 the led ripple current can be calculated as the inductor ripple current ratio flowing into the output impedance using th e laplace transform (see figure 11 ): equation 19 where the term 8/ ? 2 represents the main harmonic of th e inductor current ripple (which has a triangular shape) and ? i l is the inductor current ripple. equation 20 so l value can be calculated as: equation 21 where t off is the off-time of the embedded high switch, given by 1-d. as a consequence, the lower the inductor value (so the higher the curren t ripple), the higher the c out value would be to meet the specifications. a general rule to dimension l value is: equation 22 finally the required output capacitor value can be calculated equalizing the led current ripple specification with the module of the fourier transformer (see equation 19 ) calculated at f sw frequency. equation 23 example (see section : example ): v in = 12 v, i led = 700 ma, ? iled /i led = 2%, v fw_led = 3.5 v, n led = 2 the output capacitor value must be dimensioned according to equation 23 . finally, given the selected inductor value, a 2.2 f ceramic capacitor value keeps the led current ripple ratio lower than 2% of the nominal current. an output ceramic capacitor type (negligible esr) is suggested to minimize th e ripple contribution given a fixed capacitor value. i ripple s ?? ? 8 ? 2 ----- - ? i l 1 s esr c out ?? + ?? ?? 1sr s esr n led r led ? ++ ?? c out ?? + ---------------------------------------------------------------------------------------------------------- - = ? i l v out l -------------- t off ? n led v fw_led 100mv + ? l ----------------------------------------------------------------- - t off ? == l n led v fw_led 100mv + ? ? i l ----------------------------------------------------------------- - t off ? n led v fw_led 100mv + ? ? i l ----------------------------------------------------------------- - 1 n led v fw_led 100mv + ? v in ----------------------------------------------------------------- - ? ?? ?? ? == ? i l i led ----------- 0,5 ? i ripple s=j ? ? ?? ? i ripple_spec ? =
application information st1cc40 22/37 docid18279 rev 5 7.1.3 input capacitor the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. the input capacitor must absorb all this switching current, whose rms value can be up to the load current divided by two (worst case, with duty cycle of 50%). for this reason, the quality of these capacitors must be very high to minimize th e power dissipation generated by the internal esr, thereby improving system relia bility and efficiency. the critic al parameter is usually the rms current rating, which must be higher than the rms current flowing through the capacitor. the maximum rms input current (flowing through the input capacitor) is: equation 24 where ? is the expected system efficiency, d is the duty cycle and i o is the output dc current. considering ? = 1, this function reaches its maximum value at d = 0.5 and the equivalent rms current is equal to i o divided by 2. the maximum and minimum duty cycles are: equation 25 and equation 26 table 6. inductor selection manufacturer series inductor value ( h) saturation current (a) wrth elektronik we-hci 7040 1 to 4.7 20 to 7 we-hci 7050 4.9 to 10 20 to 4.0 coilcraft xpl 7030 2.2 to 10 29 to 7.2 i rms i o d 2d 2 ? ? -------------- - ? d 2 ? 2 ------ - + ? = d max v out v f + v inmin v sw ? ------------------------------------ - = d min v out v f + v inmax v sw ? -------------------------------------- =
docid18279 rev 5 23/37 st1cc40 application information 37 where v f is the freewheeling diode forward voltage and v sw the voltage drop across the internal pdmos. considering the range d min to d max , it is possible to determine the max. i rms going through the input capacitor. capacitors that can be considered are: electrolytic capacitors : these are widely used due to their low pric e and their availabilit y in a wide range of rms current ratings. the only drawback is that, considering ripp le current rating requirements, they are physically larger than other capacitors. ceramic capacitors : if available for the required value and volt age rating, these capacitors usually have a higher rms current rating for a given ph ysical dimension (due to very low esr). the drawback is the considerably high cost. tantalum capacitors: small tantalum capacitors with very low esr are becoming more available. however, they can occasionally burn if subjecte d to very high current during charge. therefore, it is recommended to avoid this ty pe of capacitor for the input filter of the device as they may be stressed by a hi gh surge current when connected to the power supply. in case the selected capacito r is ceramic (so neglecting th e esr contribution), the input voltage ripple can be calculated as: equation 27 7.2 layout considerations the layout of switching dc-dc converters is very important to minimize noise and interference. power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. high impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as po ssible from the high current paths. a layout example is provided in figure 13 . the input and output loops are minimized to avoid radiation and high frequency resonance problems. the feedback pin to the sensing resistor path must be designed as short as possible to avoid pick-up noise. another impo rtant issue is the groun d plane of the board. since the package has an exposed pad, it is very important to connect it to an extended ground plane in order to reduce the thermal resistance junction-to-ambient. table 7. list of ceramic capacitors for the st1cc40 manufacturer series capacitor value ( f) rated voltage (v) taiyo yuden umk325bj106mm-t 10 50 murata grm42-2 x7r 475k 50 4.7 50 v in pp i o c in f sw ? ----------------------- 1 d ? --- - ? ?? ?? d ? d ? --- - 1d ? ?? ? + ? =
application information st1cc40 24/37 docid18279 rev 5 to increase the design noise immunity, different signal and power ground should be implemented in the layout (see section 7.5: application circuit ). the signal ground serves the small signal components, the device analog ground pin, the exposed pad and a small filtering capacitor connected to the v ina pin. the power ground serves the device ground pin and the input filter. the different grounds are connected underneath the output capacitor. neglecting the current ripple contribution, th e current flowing through this component is constant during the switching activity and so this is the cleanest ground point of the buck application circuit. figure 13. layout example 7.3 thermal considerations the dissipated power of the device is tied to three different sources: ? conduction losses due to the r ds(on) , which are equal to: equation 28 where d is the duty cycle of the application. note that the duty cycle is theoretically given by the ratio between v out (n led ?? v led + 100 mv) and v in , but in practice it is substantially higher than this value to compensate for the losses in the overall ap plication. for this reason, the conduction losses related to the r ds(on) increase compared to an ideal case. p on r rdson_hs i out ?? ? 2 d ? = p off r rdson_ls i out ?? ? 2 1d ? ?? ? =
docid18279 rev 5 25/37 st1cc40 application information 37 ? switching losses due to turning on and off. these are derived using equation 29 : equation 29 where t rise and t fall represent the switching times of the power element that causes the switching losses when driving an inductive load (see figure 14 ). t sw is the equivalent switching time. figure 14. switching losses quiescent current losses. equation 30 example (see section : example ): v in = 12 v, v fw_led = 3.5 v, n led = 2, i led = 700 ma the typical output voltage is: equation 31 r dson_hs has a typical value of 95 m ? and r ds(on)_ls is 69 m ? at 25 c. for the calculation we can estimate r ds(on)_hs = 140 m ? and r ds(on)_ls = 100 m ?? as a consequence of t j increase during the operation. t sw_eq is approximately 12 ns. i q has a typical value of 1.5 ma at v in = 12 v. p sw v in i out t rise t fall + ?? 2 ---------------------------------------- - f sw v in = i out t sw_eq f sw ?? ? ?? ? = am14826v1 p q v in i q ? = v out n led v fw_led v fb + ? 7,1v ==
application information st1cc40 26/37 docid18279 rev 5 the overall losses are: equation 32 equation 33 the junction temperature of the device is: equation 34 where t a is the ambient temperature and rth j-a is the thermal resistance junction-to- ambient. the junction-to-ambient (rth j-a ) thermal resistance of the device assembled in hso8 package and mounted on the board is about 40 c/w. assuming the ambient temperature is around 40 c, the estimated junction temperature is: equation 35 7.4 short-circuit protection in overcurrent protection mode, when the peak current reaches the current limit threshold, the device disables the power element and it is able to reduce the conduction time down to the minimum value (approximately 100 nsec typ. ) to keep the inductor current limited. this is the pulse-by-pulse current lim itation to implement the constant current protection feature. in overcurrent condition, the duty cycle is stro ngly reduced and, in most applications, this is enough to limit the switch current to the current threshold. the inductor current ripple during on and off phases can be written as: ? on phase equation 36 ? off phase equation 37 where dcr l is the series resistance of the inductor. p tot r ds(on)_hs i out ?? ? 2 dr ds(on)_ls i out ?? ? 2 1d ? ?? ? v in i out f sw t sw ??? v in i q ? +++ ? = p tot 0,14 0,7 2 0,6 0,1 0,7 2 0,4 ?? 12 + 0,7 12 10 9 ? 850 10 3 12 1,5 10 3 ? ?? + ??? ? ? + ?? 205mw ? = t j t a rth ja ? p tot ? + = t j 60 0,205 40 68 ? c ? ? + = i l ton ? v in v out ? dcr l r ds(on) hs + ?? i ? ? l ------------------------------------------------------------------------------------------------ - t on ?? = i l ton ? v out dcr l r ds(on) ls + ?? i ? + ?? ? l ----------------------------------------------------------------------------------------- t off ?? =
docid18279 rev 5 27/37 st1cc40 application information 37 the pulse-by-pulse current limitation is effective in implementing constant current protection when: equation 38 from equation 36 and equation 37 we can gather that the implementation of the constant current protection becomes more critical the lower the v out is and the higher v in is. in fact, in short-circuit condition the volta ge applied to the inductor during the off-time becomes equal to the voltage drop across parasitic components (typically the dcr of the inductor and the r ds(on) of the low-side switch) since v out is negligible, while during t on the voltage applied at the inductor is maxi mized and it is approximately equal to v in . in general, the worst case scenario is heavy short-circuit at the output with maximum input voltage. equation 36 and equation 37 in overcurrent conditions can be simplified to: equation 39 considering t on that has already been reduced to its minimum. equation 40 where t sw = 1 /f sw and considering the nominal f sw . at higher input voltage, ? i l ton may be higher than ? i l toff and so the inductor current may escalate. as a consequence, the system typically meets equation 38 at a current level higher than the nominal value thanks to the increased voltage drop across stray components. in most of the application condit ions the pulse-by-pulse current limitation is effective to limit the inductor current. whenever the current escalates, a second level current protection called ?hiccup mode? is enabled. hiccu p protection offers an additional protection against heavy short-circuit condition at very high input voltage even considering the spread of the minimum conduction time of the power el ement. if the hiccup current level (6.2 a typ.) is triggered, the switching acti vity is prevented for 12 cycles. figure 15 shows the operation of the constant cu rrent protection when a short-circuit is applied at the output at the maximum input voltage. i l ton ? i l toff ? = dcr r i v i l ton ? v in dcr l r ds(on) hs + ?? i ? ? l ------------------------------------------------------------------------- t on min ?? v in l -------- - 90ns ?? ? = i l toff ? dcr l r ds(on) ls + ?? ? i ? l --------------------------------------------------------------- t sw 90ns ? ?? dcr l r ds(on) ls + ?? ? i ? l --------------------------------------------------------------- 1,18 ? s ?? ? =
application information st1cc40 28/37 docid18279 rev 5 figure 15. constant current protection triggering hiccup mode 7.5 application circuit figure 16. demonstration board application circuit am12814v1 vljqdo*1' srzhu*1' q)9 & 9/(' x9 & 5 . 9,1 *1' 5 10 56 ',0 9,1b$ ',0 )% $*1' 3*1' 6: 9,1b6: (3 67&& x9 & / / x+ -3 9/(' $0y
docid18279 rev 5 29/37 st1cc40 application information 37 figure 17. pcb layout (component side) vfqfpn8 package table 8. component list reference part number description manufacturer c1 100 nf 50 v (size 0805) c2 grm31cr61e106ka12l 10 f 25 v (size 1206) murata c3 grm21br71e225ka73l 2.2 f 25 v (size 0805) murata r1 4.7 k ?? 5% (size 0603) r2 not mounted rs erj14bsfr15u 0.15 ??? 1% (size 1206) panasonic l1 xal6060-223me 22 h i sat = 5.6 a (30% drop) i rms = 6.9 a (40 ? c rise) (size 6.36 x 6.56 x 6.1 mm) coilcraft
application information st1cc40 30/37 docid18279 rev 5 figure 18. pcb layout (bottom side) vfqfpn8 package figure 19. pcb layout (component side) so8 package it is strongly recommended that the input capacito rs are to be put as close as possible to the relative pins, see c1 and c2.
docid18279 rev 5 31/37 st1cc40 application information 37 figure 20. pcb layout (bottom side) so8 package
typical characteristics st1cc40 32/37 docid18279 rev 5 8 typical characteristics figure 21. soft-start figure 22. inhibit operation figure 23. thermal shutdown protection figure 24. hiccup current protection figure 25. ocp blanking time figure 26. current regulation am12818v1 am12819v1 am12820v1 am12821v1 130 ns typ. am12822v1 vin 12v vled 7v am12823v1
docid18279 rev 5 33/37 st1cc40 package information 37 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com. ecopack is an st trademark. figure 27. vfqfpn8 (4 x 4 x 1.08 mm) package outline table 9. vfqfpn8 (4 x 4 x 1.08 mm) package mechanical data symbol dimensions (mm) min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 a3 0.20 b 0.23 0.30 0.38 d 3.90 4.00 4.10 d2 2.82 3.00 3.23 e 3.90 4.00 4.10 e2 2.05 2.20 2.30 e0.80 l 0.40 0.50 0.60
package information st1cc40 34/37 docid18279 rev 5 figure 28. so8-bw package outline table 10. so8-bw package mechanical data symbol dimensions (mm) min. typ. max. a 135 1.75 a1 0.10 0.25 a2 1.10 1.65 b 0.33 0.51 c 0.19 0.25 d (1) 1. dimension d does not include mold flas h, protrusions or gate burrs. mold flash, protrusions or gate burrs shouldn?t exceed 0.15 mm (.006 inch) in total (both sides). 4.80 5.00 e 3.80 4.00 e1.27 h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 k 0 (min.), 8 (max.) ddd 0.10
docid18279 rev 5 35/37 st1cc40 ordering information 37 10 ordering information table 11. ordering information order code package packaging ST1CC40PUR vfqfpn8 4 x 4 8l tape and reel st1cc40dr so8-bw tape and reel
revision history st1cc40 36/37 docid18279 rev 5 11 revision history table 12. document revision history date revision changes 04-mar-2011 1 initial release. 21-jun-2011 2 updated coverpage 18-oct-2012 3 pin 2 operation has been updated: figure 1 and ta ble 1 have been updated accordingly. figure 19 and figure 20 have been added. minor text changes to improve the readability. status promoted from preliminary to production data. 04-mar-2013 4 updated table 9: vfqfpn8 (4 x 4 x 1.08 mm) package mechanical data and section 7.1.2: inductor and output capacitor selection . minor text changes to improve the readability. 18-jun-2013 5 unified package names in the whole document. updated table 2 (changed ?operating junction temperature range? from -40 to 125 c to -40 to 150 c). updated table 4 (updated data of i qst-by symbol). updated section 7.2 (replaced vcc by v ina ) . updated section 9 (reversed order of figure 27 and table 9 , figure 28 and table 10 , minor modifications). minor corrections throughout document.
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